Design and Measurement of Neuron circuit for a Mixed-Signal 65-nm CMOS Wafer-Scale Neuromorphic Substrate

by Syed Ahmed Aamir

Tuesday Mar 22, 2016, 10:00 AM → 11:00 AM Europe/Berlin

114 (IPE)

Neuromorphic circuits strive to provide fundamentally different form of computing architectures, strongly inspired from the neuro-biological computing paradigm of the nervous system. Microchips designed in the CMOS technology, provide high integration for fundamental building blocks known through neuroscientific evidence, and can be configured to implement spiking neural networks. Further, they need to be energy-efficient, reconfigurable, massively parallel, and possibly even fault tolerant. We have recently measured our latest mixed-signal HICANN-DLS neuromorphic prototype chip, designed in 65-nm CMOS technology. The chip integrates an array of neuron and synapse circuits, along with analog memory cells used to tune individual/global voltage and current biases. It further integrates a SIMD processor for implementing spike-based learning rules. This talk focuses on the design and measurement of the neuron circuit. The neuron circuits implement an analog accelerated leaky integrate-and-fire model. Each neuron integrates input incoming current from a multitude of incoming synapse circuits onto its membrane, and provides a digital output, once the integrated voltage crosses a fixed threshold. A read-out buffer provides us with an off-chip membrane voltage.