Name: Topical Workshop: FPGAs in Research - Applications, Technologies and Tools
Start: 2012-12-03T12:00:00+01:00
End: 2012-12-04T16:00:00+01:00
Location: Zentralinstitut für Elektronik, Forschungszentrum Jülich

Topical Workshop: FPGAs in Research - Applications, Technologies and Tools

from Monday, December 3, 2012 (12:00 PM) to Tuesday, December 4, 2012 (4:00 PM)

Monday, December 3, 2012

12:00 PM Lunch
Lunch
12:00 PM - 1:00 PM
Room: Room 110 in Building 2.5
1:00 PM
1:00 PM - 3:15 PM
Room: Room 110 in Building 2.5
Contributions

1:00 PM Introduction - Harald Kleines (Forschungszentrum Jülich)

1:05 PM Zentralinstitut für Elektronik - Facts, Figures, Tasks & Topics - Harald Kleines (Forschungszentrum Jülich)

1:20 PM FPGA-basierte digitale Gamma-Spektroskopie zur Überwachung der Umweltradioaktivität - Markus Dambacher (FMF)

2:00 PM FPGA-based Tomographiecameras - Jörg Burmester (HZG) Jörn Plewka (HZG)

2:25 PM FPGA-based algorithm for center of gravity calculation of clustered signals using RAM for history storing - Andriy Ushakov (Helmholtz zentrum Berlin)

2:50 PM Development of a FPGA based DAQ for digital SiPM‘s using USB 3.0 - Holger Noeldgen (Forschungszentrum Juelich)
3:15 PM Coffee Break
Coffee Break
3:15 PM - 3:45 PM
Room: Room 110 in Building 2.5
3:45 PM
3:45 PM - 5:25 PM
Room: Room 110 in Building 2.5
Contributions

3:45 PM The ATCA based Compute Node and its application in the Belle II PXD-DAQ - Bjoern Spruck (Uni Gießen)

4:10 PM The Juelich Digital Readout System for $\overline{\text{P}}$anda development - Simone Esch (Forschungszentrum Jüich)

4:35 PM Data Concentrator for the Belle II DEPFET Pixel Detector - Michael Schnell (University of Bonn)

5:00 PM Firmware-Entwicklung für die ATLAS IBL BOC Karte - Marius Wensing (Bergische Universität Wuppertal)
7:00 PM Dinner
Dinner
7:00 PM - 10:00 PM
Room: Große Rurstraße 94
Tuesday, December 4, 2012
9:00 AM
9:00 AM - 10:30 AM
Room: Room 110 in Building 2.5
Contributions

9:00 AM High Level Synthesis with Xilinx HLS - Eugen Krassin (plc2)
10:30 AM Coffee Break
Coffee Break
10:30 AM - 11:00 AM
Room: Room 110 in Building 2.5
11:00 AM
11:00 AM - 12:15 PM
Room: Room 110 in Building 2.5
Contributions

11:00 AM FPGA Programming Methods - An Overview - Diana Goehringer (KIT)

11:25 AM Matlab/Simulink and HDL-coder - Renhai Xiong (Forschungszentrum Jülich)

11:50 AM Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications - Sergey Suslov (Research Center Juelich, Central Institute for Electronics)
12:15 PM Lunch
Lunch
12:15 PM - 1:15 PM
Room: Room 110 in Building 2.5
1:15 PM
1:15 PM - 3:20 PM
Room: Room 110 in Building 2.5
Contributions

1:15 PM Field Programmable Gate Array Based Data Digitisation with Commercial Elements - Cahit Ugur (GSI)

1:40 PM An FPGA Platform for Ultra-fast Data Acquisition - Michele Caselle (KIT)

2:05 PM FPGA Oriented HW/FW Development in FEA DESY - Frantisek krivan (DESY)

2:30 PM FPGA- Framework development for a MicroTCA system - Qingqing Xia (DESY)

2:55 PM Dynamische Re -Konfiguration eines FPGAs mittels internem Kontroller - Markus Dick (Forschungszentrum Juelich)

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