Real-time high-performance readout system (100 Tb/s) for the CMS track trigger High Energy Physics detectors
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Lecture to the Doctoral thesis from Luis Ardila on the topic: Real-time high-performance readout system (100 Tb/s) for the CMS track trigger High Energy Physics detectors
The high-luminosity (HL) upgrade of the LHC in 2025 will increase the simultaneous proton-proton collisions from the current average of 25 to up to 200 every 25 ns. Each collision produces an equivalent data throughput of about 300 Tb/s, an amount impossible to store for offline analysis. The HL upgrade will completely replace the CMS silicon tracker with one purposely built to discriminate on-module the charged particles whose transverse momentum (pT) is larger than 2 GeV, therefore selecting only about 10% of all hits. These high-energetic hits are forwarded to the off-detector electronics and used to perform real-time track reconstruction under 4 μs of latency. For the first time in any particle physics experiment, the reconstructed tracker primitives will be included in the first-level (L1) trigger with the aim of maintaining the trigger rate of CMS below 750 kHz or an equivalent 5.4 Tb/s to the high-level trigger (HLT).
This presentation includes various fundamental developments to demonstrate the feasibility of reconstructing tracks under the tight latency requirements of the HL CMS L1-trigger system. The Time-multiplexed Track Trigger (TMTT) reconstruction algorithm has four processing stages, two of which were implemented in Hardware Description Language (HDL) by the author and are detailed in this presentation. Optimizations of such algorithms for increased clock frequency operation and resource utilization optimization are presented. The overall reconstruction efficiency of the entire processing chain will also be discussed. Furthermore, the development of specialized hardware utilizing the Advanced Telecommunications Computing Architecture (ATCA) form factor will be detailed. The board has an enormous processing capability which greatly exceeds the requirements of the HL outer tracker. It implements a novel slow-control solution by combining the Intelligent Platform Management Controller (IPMC), a Linux slow-control software, and an FPGA for custom slow-control tasks in a single Zynq Ultrascale+ (US+) System-on-Chip (SoC) module. Currently, this board offers the most cost effective alternative to implement the HL-CMS tracker back-end electronics system.
Lecture language: English