Cross-Chip Dynamic Function eXchange for the Initialization of Heterogeneous Multi-FPGA Systems
by
https://kit-lecture.zoom-x.de/j/67140340939?pwd=bmhGY3ZYbm93RnBMd2FjQTV2NVF4UT09
Zoom + R413
Master thesis presentation of Hendrik Krause: Cross-Chip Dynamic Function eXchange for the Initialization of Heterogeneous Multi-FPGA Systems.
The presentation will be held in hybrid format, you can either join in room 413 or on zoom.
Abstract:
Motivated by the need for a modular, multi-device controller for superconducting quantum processors, this thesis presents a new initialisation and reconfiguration framework for heterogeneous Multi-FPGA-Systems. The controller consists of a Radio Frequency System on a Chip (RFSoC) to read and manipulate quantum bits (qubits) and multiple peripheral FPGAs to control the entanglement. While motivated by a system based on a RFSoC, the developed concept applies to arbitrary configurations combining one or multiple Zynq MPSoCs with additional FPGAs. The framework is based on the concept of Dynamic Function eXchange (DFX), which is extended to reconfigure multiple FPGAs from a single MPSoC through existing cross chip AXI based communication infrastructure. Most of the client FPGAs fabric can be dynamically reconfigured, because only a small static design is needed to initialise the interface and to provide access to the configuration memory. Device-tree overlays are used in a two-stage approach to integrate additional FPGAs at runtime in the operating system of the MPSoC and to trigger their initialisation or reconfiguration. This enables highly modular and runtime scalable systems that support the addition or removal of entire FPGAs at runtime. Furthermore, it enables automatic initialisation and adaptation to changing requirements as well as dynamic updates in the field. Address masking on the Zynq MPSoC is used to address the AXI address space of individual client FPGAs, allowing to deploy the same design on every FPGA without address conflicts. The framework was implemented into the existing yocto and logicc based build system at the EPS/SDR group at the Institute for Data Processing and Electronics (IPE) at the Karlsruhe Institute of Technology (KIT) and evaluated on AMD Xilinx ZCU102 and VCU118 development boards.
Language: German