Präsentation von zwei Abschlussarbeiten
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Präsentation der Bachelorarbeit von Clara Solms: Entwicklung eines Produktionstests für Serenity-S1 ATCA Karten
Kurzfassung:
Ziel dieser Arbeit ist es Testfälle für das Serenity-S1 zu untersuchen und einen End-Of-Line- Test zu planen. Darauf folgend soll der Test und ein Testprotokoll entwickelt werden und schließlich auf den Piloten-Boards validiert werden. Hierbei sollte der Test so automatisch wie möglich sein. Er sollte auf der KRIA laufen und so wenig wie möglich funktionierende Hardware voraussetzen.
Abstract:
The Serenity-S1 is a back-end processor card of which 721 will be used in the phase-2 upgrade of the CMS experiment. It will be used across many subsystems with the most cards being used by the outer tracker and HGCAL. A main processing FPGA is performing algorithms on data that are received from up to 120 FireFly optical links at the speed of up to 25 Gb/s each and can be transmitted over according transmitting links. The card is controlled by a KRIA SoM that is based on a Zynq Utrascale+ System on Chip. Currently the pilot production is running and the boards are evaluated. In the end of 2024, the pre-production of 50 boards will start and by the end of 2025, all 721 cards should be produced. An end-of-line production test needs to be developed, that will test the board for possible manufacturing errors. The test should require as little manual work as possible and should mostly run automatic. The platform uses a custom management shell, which has python bindings, therefore a python script should be used to perform the test and document the results. In this thesis, an automated test should be developed that can be run on the KRIA on the Serenity-S1. The test should assume as little working hardware as possible and should bring up the board in a safe manner (e.g. detecting shorts before powering the corresponding rails)
Vortragssprache: Deutsch
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Bachelor thesis presentation of Nick Fruechtenicht: Design and Implementation of a Resource Efficient and Flexible Digital Up Converter for Qubit Control Electronics
Abstract:
Direct digital synthesis (DDS) is widely used in modern qubit control systems for superconducting quantum computers. As an important part in the digital signal processing chain of qubit control, a digital up converter (DUC) is used to shift a digitally generated baseband signal to radio frequencies. The standard DUC on AMD's RFSoCs restricts the usable bandwidth by about 20% for sampling frequencies above 7 GHz. To overcome these shortcomings, a custom DUC was designed and implemented. The custom DUC has no restricted bandwidths and offers an SFDR between 20 dBc and 50 dBc, depending on the baseband frequency. A highly flexible and resource efficient implementation of the DUC makes the parallel control of up to 13 qubits possible.
Lecture language: English
Frank Simon