Lessons learned: Factory Acceptance Test for the CMS Phase-2 back-end card Serenity-S1

by Mr Hendrik Krause (IPE)

Thursday Jan 29, 2026, 2:00 PM → 3:00 PM Europe/Berlin

Seminarraum EG (IPE)

The Serenity-S1, a versatile FPGA-based processing card using the ATCA form factor, has been developed for part of the CMS phase-2 upgrade by the Serenity collaboration. It has been widely adopted by various subdetector systems for the back-end data processing and a total demand of 777 boards has now been accumulated. This talk will explain the ideas behind the 3-stage testing process. The Factory Acceptance Test (FAT) is the 1st stage, including the compromises made and the resulting benefits/risks. It will detail the implementation of the FAT for the Serenity- S1 board and present the results and lessons learnt from using it during the extended pilot and pre-production phases.