Lessons learned: Factory Acceptance Test for the CMS Phase-2 back-end card Serenity-S1

by Mr Hendrik Krause (IPE)

Thursday Mar 5, 2026, 2:00 PM → 3:00 PM Europe/Berlin

Seminarraum EG + Zoom (IPE)

The Serenity-S1, a versatile FPGA-based processing card using the ATCA form factor, has been developed for part of the CMS phase-2 upgrade by the Serenity collaboration. It has been widely adopted by various subdetector systems for the back-end data processing and a total demand of 777 boards has now been accumulated.
This talk presents the multi-stage quality assurance (QA) strategy used for the Serenity-S1, with a particular focus on the Factory Acceptance Test (FAT), a new development that enables automated functional testing directly at the production site. The presentation will discuss the design choices and implementation of the FAT, share results and lessons learned from its deployment and usage during pre-production and early main-production phases and highlight how these concepts can be extended to other boards of similar complexity.