Speaker
Description
Due to high prototyping costs, modern semiconductor design relies on extensive signoff simulations to verify the electrical
performance and reliability of complex integrated circuits before production.
As technology nodes continue to shrink and circuit complexity grows, the computational requirements of these simulations can
become a significant bottleneck in the design flow.
Industry-standard design tools such as the Cadence Spectre Circuit Simulator keep up with this trend by introducing support for high-performance computing (HPC): Since 2019 parallelization on up to 256 CPU cores is supported, in 2023 the support of NVIDIA enterprise GPUs was introduced.
While commercial design companies typically can afford to own sufficient HPC resources to benefit from these features,
this is not feasible for small to medium-sized research groups in the field of microelectronics. The costs of purchasing high CPU and RAM compute nodes,
or enterprise grade GPUs as well as the effort in setting up and maintaining an automated workload distribution would not be justifiable for the one last
signoff simulation at the end of a design process. For those few occasions, the use of on-demand external cloud resources is way more reasonable as it allows to share HPC resources with other groups and access them only when needed.
A typical design flow in electronic design starts with short and interactive simulations on local workstations. The designers need immediate feedback to refine circuit parameters. This would not be suited for HPC workloads and queues. As a design evolves and is put together from many partial designs, grows bigger and simulations on multi-core workstations take too long. It is then desirable to use clusters like bwHPC NEMO2 and thus our group established a workflow for compute-intensive signoff simulations.
Scaling out to external cloud infrastructure with traditional load sharing paradigms requires a careful setup of the toolchain to meet challenges such as
different remote usernames, missing shared NFS file space, incompatible job scheduling, missing graphical remote desktop resources,
missing EDA software, missing PDK, license acquisition and non-disclosure agreements.
Additionally, we adapted to cloud specific constraints such as wall-clock-time limits or the need for regular two factor authentication.
By this we managed to successfully deliver our simulations to the bwHPC NEMO2 cluster and benefit from the large amount of high-end compute resources there. We observed simulation speed-ups of up to 2.1x / 2.5x on the CPU / H200 partition. GPU Cloud support was just recently released by Cadence and we expect to see even higher speed-ups there by fine-tuning the allocation of resources. The significant reduction of simulation time enables more comprehensive chip validation, allows to find design errors which we could not simulate before and improves the quality of our tape-outs.